1. Field of the Invention
The present invention relates to the field of integrated circuits (IC). More specifically, the present invention relates to methods and apparatuses associated with processing an IC design.
2. Background Information
Because of the ever increasing complexity of IC designs, most modern IC designs are expressed in terms of hierarchically organized design cells. For example, an exemplary IC may be expressed in terms of a collection of placements of design cells A, B, C, . . . and various xe2x80x9cinterconnectingxe2x80x9d geometric elements, whereas design cell A may in turn be likewise expressed as a collection of placements of design cells A1, A2, . . . , and various xe2x80x9cinterconnectingxe2x80x9d geometric elements within cell A, design cell B expressed as a collection of placements of design cells B1, B2, . . . , and various xe2x80x9cinterconnectingxe2x80x9d geometric elements within cell B, and so forth.
Additionally, prior to fabrication (especially those IC designs fabricated using sub-micron processes), various verification operations, including but not limited to design rule checks (such as spacing), RC analysis, and so forth, are performed to ensure the fabricated IC will function as designed. In order to verify a particular design cell, in view of the hierarchical nature of its organization, it is necessary to verify the context independent and context dependent portions of the design cell separately. The context dependent portion of the design cell is promoted upward recursively until it is a part of the context independent portion of a higher level design cell, a process known as xe2x80x9cselective promotionxe2x80x9d.
In order to facilitate efficient performance of these operations, various design cell injection techniques are known and practiced in the art to reduce the amount of selective promotions. Design cell injection is a process by which a design cell is re-expressed in terms of a number of artificially-created design cells. For example, a design cell A having placements of design cells A1, A2, A3, A4 and A5 may be re-expressed in terms of placements of artificially created design cells A10 and A11, where artificially created design cell A10 is comprised of placements of design cells A1 and A2, and artificially created design cell A11 is comprised of placements of design cells A3, A4 and A5.
More specifically, Applicant is aware of three known design cell injection techniques. They are xe2x80x9chomogenousxe2x80x9d injection, xe2x80x9coverlappingxe2x80x9d injection and xe2x80x9cheterogeneousxe2x80x9d injection. As will be readily apparent from the description to follow, these three prior art techniques share a common characteristic in that they are xe2x80x9cpattern basedxe2x80x9d, i.e. each of the techniques is tailored for design cells having particular inter-cell relationship characteristics.
Under homogeneous injection, an exemplary design cell Z comprised of an array placement of identical design cell A, Aij (i.e. different instances of design cell A), where i and j both equal 1 through 4, will be re-expressed as shown in FIG. 1. That is, adjacent instances, e.g. A11 and A12, A13 and A14, will first be combined to form instances of design cell B, B11 and B12. Then, instances of design cell B, B11 and B12 etc. will be combined to form instances of design cell C, C1, C2 and so forth. Eventually, design cell Z is re-expressed in terms of instances of design cell D, D1 and D2, where design cell D is comprised of placements of design cell C. Design cell C in turn is comprised of instances of design cell B, B11 and B12, B21 and B22, B31 and B32 and B41 and B42 respectively. The technique, i.e. homogeneous injection, is commonly applied to IC such as a memory chip.
Under overlapping injection, an exemplary design cell Zxe2x80x2 comprised of placements of design cell Axe2x80x2, Axe2x80x2ij (i.e. different instances of design cell Axe2x80x2), where i and j both equal 1 through 4, and having xe2x80x9csuperimposedxe2x80x9d placements of design cell Bxe2x80x2, Bxe2x80x2kl, where k and l both equal 1 through 2, will be re-expressed as shown in FIG. 2. That is, a group of design cell placements exhibiting a particular structural pattern, e.g. Axe2x80x211, Axe2x80x212, Axe2x80x221, Axe2x80x222 and Bxe2x80x211, Axe2x80x213, Axe2x80x214, Axe2x80x223, Axe2x80x224 and Bxe2x80x212, will first be combined to form instances of design cell Cxe2x80x2, Cxe2x80x211 and Cxe2x80x212. Then, design cell placements Cxe2x80x211 and Cxe2x80x212 etc. will be combined to form instances of design cell Dxe2x80x2, Dxe2x80x21 and Dxe2x80x22. So, design cell Zxe2x80x2 is ultimately re-expressed in terms of instances of design cell Dxe2x80x2, Dxe2x80x21 and Dxe2x80x22. The technique, i.e. overlapping injection, is commonly applied to IC comprised of gate arrays.
Under heterogeneous injection, an exemplary design cell Zxe2x80x3 comprised of a number of xe2x80x9cstandardxe2x80x9d cells will be re-expressed with new design cells replacing a group of standard cells having a distinct structural organization, as shown in FIG. 3. For example, exemplary design cell Zxe2x80x3 having a number of placements of design cells Bxe2x80x3, Cxe2x80x3 and Dxe2x80x3, will be re-expressed in terms of multiple placements of design cell Exe2x80x3, where design cell Exe2x80x3 is comprised of placements of design cells Bxe2x80x3, Cxe2x80x3 and Dxe2x80x3. The technique, i.e. heterogeneous injection, is commonly applied to IC comprised of a large number of xe2x80x9cstandardxe2x80x9d cells. [The term xe2x80x9cstandardxe2x80x9d cell, as understood by those skilled in the art, refers to xe2x80x9cbuilding blockxe2x80x9d circuitry that are frequently reused in the design of an IC. They are often supplied by EDA tool vendors.]
While these techniques have worked well for IC designs having the above enumerated inter-cell relationship characteristics, experience has shown that their contributions to improving the efficiency for verifying IC designs with a large number of xe2x80x9cflatxe2x80x9d design cells are limited. Thus, additional approaches to further improve the efficiency for processing such IC designs are desired.
An EDA tool is provided with the ability to re-express a design cell of an IC design in terms of placements of a number of newly formed intervening constituent design cells, the IC design having a number of hierarchically organized placements of design cells. The new intervening constituent design cells are formed in accordance with a number of metrics profiling placements of the original constituent design cells of the design cell. The EDA tool is also provided with the ability to determine the metrics.
In one embodiment, the metrics are weights reflective of at least placement activities associated with row and column coordinates of the design cell. The EDA tool first determines these weights, and then uses the determined weights to select a subset of the row/column coordinates as cut line coordinates to logically partition the design cell into a number of regions. Finally, the EDA tool selectively groups contents of the selected design cell to form the new intervening design cells based on the contents"" relations to the formed regions.
In one embodiment, the EDA tool is a design verification tool for use to verify the IC design prior to fabrication.